Minutes, IBIS Quality Committee 22 May 2007 11-12 AM EST (8-9 AM PST) ROLL CALL Adam Tambone * Barry Katz, SiSoft Benny Lazer Benjamin P Silva * Bob Cox, Micron * Bob Ross, Teraspeed Consulting Group Brian Arsenault * David Banas, Xilinx Eckhard Lenski, Siemens Eric Brock Gregory R Edlund Hazem Hegazy John Figueroa John Angulo, Mentor Graphics Katja Koller, Siemens Kevin Fisher * Kim Helliwell, LSI Logic Lance Wang, IOMethodology Lynne Green * Mike LaBonte, Cisco * Mike Mayer, SiSoft * Moshiul Haque, Micron Technology Peter LaFlamme Radovan Vuletic, Qimonda Robert Haller, Enterasys * Roy Leventhal, Leventhal Design & Communications Sherif Hammad, Mentor Graphics * Todd Westerhoff, SiSoft Tom Dagostino, Teraspeed Consulting Group Kazuyoshi Shoji Sadahiro Nonoyama Everyone in attendance marked by * NOTE: "AR" = Action Required. -----------------------MINUTES --------------------------- Mike LaBonte conducted the meeting. AR Review: - Moshiul send a datasheet for SSTL2 - Done - Mike invite Barry Katz to next meeting for [Receiver Thresholds] discussion - Done - All review IBIS [Receiver Thresholds] and SSTL2 for next call - Done - Mike change 3.2.5 to exempt RLC requirement when [Package Model] present - Done - Mike delete 3.3.3 from IQ spec - Done - Roy clarify 3.3.2 - Done - Mike change 3.3.4 to require a comment for unique +/- diff pair models - Done New items: - David: apologies for being vendor specific Discussion of [Receiver Thresholds]: - David: Should Vth_min and Vth_max be used to demarcate minimum etch delay? - Mike: Vth_min and max are at typ corner - Bob C: - Min and max are an additional guard band around Vth - Specs are not clear about this - The real reference will always be Vdd/2 - In DDR all signals pseudo-differential, really single ended - Vref can move +/-18mV - DC noise adds an additional 18mV - The guard band is calculated in slew rate measurements - Actual measurements are made from Vref_dc to Vref_ac on the opposite side - Todd: - Measurments using Vinl and Vinh are pessimistic, leaving margin on the table - Bob C: - We used to leave margin on the table for slow signals - Specs guarantee that at 1V/ns the part switches - We need to add more switch delay for higher slew rates - Charge accumulation is modeled using derating - Todd: - IBIS has no slew rate derating - CMOS is measured to AC Vinh and Vinl - Timing is measured using exactly 1V/ns - David: - We can't have a zero region of uncertainty - Barry: - Setup/hold has to be measured the way it is specified - David: - We need to look at maximum uncertainty for data, and min for clock - Roy: - IBIS needs more language to cover DDR2 slew rate provisions - David: - Is slew rate uncertainty built into setup/hold? - Bob C: it is not built in - Barry: it is, by measuring at Vref - David: - We measure when clock crosses .25, data crosses .75 - Bob C: - There are differences between DDR and SDR: - DDR is AC to AC, as long as the signal remains outside DC limits - SDR is 20/80 - Todd: - There is a difference between when it switches and how timing is done - Bob C: - Single ended strobe and differential strobe are different: - Single ended is measured at specific voltages - Differential is measured at 0V - Barry: - For DDR2 ??? - Todd: - Uncertainties from IC vendors would be smaller than David's method - At reference slew rate - The IBIS spec does not cover everything needed for DDR2 - Bob C: But the simulator does not have to know it is DDR2 to use IBIS keywords - Bob R: - Gary Pratt showed how to write equations for DDR2 specs. We decided to hold a meeting next week. Some members had to leave the call Bob R: It would be nice to see the source JEDEC spec AR: Moshiul send DDR2 JEDEC spec Next meeting: 29 May 2007 11-12 AM EST (8-9 AM PST) Phone: 1.877.384.0543 or 1.800.743.7560 Passcode: 90437837 Meeting ended at 12:21 PM Eastern Time.